1. Field of the Invention
The present invention relates to an electronic circuit system having a CPU, a semiconductor memory device operated on the basis of a clock supplied from an external unit and an interface circuit permitting read and write operations for data with respect to the semiconductor memory device based on control by the CPU.
In the recent years, mass storing and high speed have been progressing for the semiconductor memory device, and specifically, in a DRAM (Dynamic Random Access Memory), such a tendency is notable.
Since the mass storing and high speed for the semiconductor memory device, there is a progressing tendency for the data transmission between the semiconductor memory device and an interface circuit or a CPU to the high speed.
2. Description of the Related Art
A description will now be given of a conventional electronic circuit system having a semiconductor memory device operating on the basis of a clock from an external unit and an interface circuit permitting read and write operations for data with respect to the semiconductor memory device based on control by the CPU.
A conventional electronic circuit system in which , a DRAM (Dynamic Random Access Memory) is, for example, used as the semiconductor memory device is shown in FIG. 1.
Referring to FIG. 1, the electronic circuit system has a CPU 101, a DRAM 102, a system LSI 103 and a clock generating circuit 104. The CPU 101 controls the read and write operations for the data with respect to the DRAM 102 (the semiconductor memory device). The DRAM 102 operates on the basis of a clock from the clock generating circuit 104 in the read and write operations for the data. The system LSI 103 operates as an interface circuit which executes the read and write operations for the data with respect to the DRAM 102 based on the control from the CPU 101. The clock generating circuit 104 generates the clock used for the DRAM 102 and the system LSI 103.
The DRAM 102 and the system LSI 103 are connected by a clock signal line, control signal lines for read and write signals and other control signals, address lines and data lines. In this example shown in FIG. 1, a number n of address lines and a number m of data lines respectively correspond to a number of bits of the capacity of the DRAM 102.
The clock generated by the clock generating circuit 104 is supplied, as a system clock, to the DRAM 102 and the system LSI 103 and used as the basis for operations in the DRAM 102 and the system LSI 103. That is, the DRAM 102 and the system LSI 103 operate in synchronism with the system clock. The former DRAM did not operate in synchronism with a clock, but operated on the basis of control signals, such as read and write signals. However, in recent DRAMs, the control signals, such as the read and write signals become definite on the basis of the system clock and an operations is started in order to execute the read and write operations for the data at a high speed.
In the conventional electronic circuit apparatus as described above, to write data in the DRAM 102, the CPU 101 sets write data and write address in an output register 106 via a CPU interface 105 in the system LSI 103. The CPU 101 then inputs a write command on-signal to a signal generating circuit 108. In the system LSI 103, the output register 106 outputs the write data, together with the write address, on the basis of the system clock. The signal generating circuit 108 activates and outputs a write signal. In the DRAM 102, the write data is written at the specified address on the basis of the system clock when the write signal is activated.
On the other hand, to read out data from the DRAM 102, the CPU 101 sets a read address in the output register 106 via the CPU interface 105 in the system LSI 103. The CPU 101 then inputs a read command on-signal to the signal generating circuit 108. In the system LSI 103, the read address is output and the signal generating circuit 108 activates and outputs a read signal. In the DRAM 102, data is read out from the specified address on the basis of the system clock when the read signal is activated. In the system LSI 103, the read data is set in an input register 107 on the basis of the system clock. In this state, the CPU 101 reads out the data from the input register 107.
In the conventional electronic circuit system, there is not a little wiring delay in the data lines connecting the DRAM 102 (the semiconductor memory device) and the system LSI 103 (the interface circuit). The wiring delay is permitted to fall within a permissible range. A circuit board is designed so that the wiring delay is as small as possible. Due to the high speed operations in the semiconductor memory device (the DRAM), there is a tendency to narrow the permissible range. Thus, it is difficult to cope with the wiring delay by only the formation of the circuit board.
When the CPU reads out data from the semiconductor memory device, the interface circuit may not read the read data due to the wiring delay in the data lines. In the same manner as in the above case, in the write operation for data with respect to the semiconductor memory device, the data may not be written in the semiconductor memory device.
Further, if there is variation of the wiring delay among the data lines connecting the semiconductor memory device and the interface circuit, the wiring delay in a part of the data lines may not fall within the permissible range. As a result, the data may not be written in the semiconductor memory device.
Accordingly, a general object of the present invention is to provide novel and useful electronic circuit system and interface circuit in which the disadvantages of the aforementioned prior art are eliminated.
A specific object of the present invention is to provide an electronic circuit system in which a CPU can accurately execute read and write operations for data with respect to a semiconductor memory device even if there are wiring delay and variation thereof in data lines.
The above objects of the present invention are achieved by an electronic circuit system comprising: a CPU; a semiconductor memory device that operates on the basis of a clock; and an interface circuit that permits read and write operations for data with respect to the semiconductor memory device under a control operation of the CPU, wherein the interface circuit comprises: a read data storage unit that stores read data from the semiconductor memory device; a write data storage unit that stores write data to be written in the semiconductor memory device; and an operation speed setting unit that sets a reading speed and a writing speed to predetermined speeds under the control operation of the CPU, wherein the CPU compares the read data in the read data storage unit and the write data in the write data storage unit.
The above predetermined speeds set by the operation speed setting unit may include a low speed corresponding to a low speed write mode and a low speed read mode and a high speed, higher than the low speed, corresponding to a high speed write mode and a high speed read mode. The read data in the read data storage unit and the write data in the write data storage unit corresponds with each other with certainty in a case where after a write operation in the low speed write mode is executed with respect to a predetermined address of the semiconductor memory device, a read operation in the low speed read mode is executed with respect to the same address of the semiconductor memory device. Operations are usually executed in the high speed write mode and the high speed read mode.
The above interface circuit may have a timing control unit that controls a delay time of the clock when the read data in the read data storage unit and the write data in the write data storage unit do not correspond with each other.
Further, the timing control unit may control the delay time of the clock for each of data lines, connecting the semiconductor memory device and the interface circuit, separately.
According to the present invention, since the reading speed and the writing speed can be set to the predetermined speeds, it can be determined, by comparing the read data and the write data obtained in the read operation and the write operation at the reading speed and the writing speed both of which are set to the predetermined speeds, whether errors have occurred in the write operation, the read operation or both the operations.
In addition, since the delay time of the clock used for the semiconductor memory device is controlled, a CPU can accurately execute read and write operations for data with respect to a semiconductor memory device even if there are wiring delay and variation thereof in data lines.
Another object of the present invention is to provide an interface circuit used in the electronic circuit system as described above.
The above objects of the present invention are achieved by an interface that permits read and write operations for data with respect to a semiconductor memory device under a control operation of a CPU, the interface circuit comprising: a read data storage unit that stores read data from the semiconductor memory device; a write data storage unit that stores write data to be written in the semiconductor memory device; and an operation speed setting unit that sets a reading speed and a writing speed to predetermined speeds under the control operation of the CPU.